The present invention relates to phase and frequency lock detection circuits, and more particularly, to three state phase frequency lock detectors.
Phase-lock loops (PLL""S) and their associated phase lock detection circuits are widely used in modern communications systems, telemetry, timing and frequency control and instrumentation systems. PLL""s are critical for communication applications where the frequency and phase of the transmitted carrier frequency contain the information to be communicated. Accordingly, providing a method whereby phase and frequency errors within the transmission carrier can be minimized is desirable. Phase coherent and frequency coherent communication systems, utilizing PLL""s to maintain phase and frequency coherency, is one method which can be utilized to minimize communication errors.
Three state phase and frequency detectors (PFD""s) provide a method of frequency and phase control whereby phase pulses are used to provide instantaneous phase information about the positive and negative phase error between a reference signal and a feedback signal. Positive phase pulses, or UP pulses, provided by the PFD indicate that the phase of the feedback signal must be advanced relative to the reference signal. Negative phase pulses, or DOWN pulses, provided by the PFD indicate that the phase of the feedback signal must be retarded relative to the reference signal. Three state lock detection circuits use the information provided by the UP and DOWN pulses to provide a lock detect signal. The lock detect signal provides information about the state of the PLL, which can be used to control the bandwidth of the PLL.
Prior art three state lock detection circuits provide information about the lock state of the PLL, however, the information is generally not available instantaneously. In general, prior art lock detection circuits lag the actual state of the PLL by several cycles. In other words, lock detect indications provided by prior art lock detection circuits are not real time. In addition, prior art lock detection circuits are severely limited by high frequency applications. Prior art lock detection circuits generally operate in the tens to hundreds of megahertz, whereas, current technology trends are demanding gigahertz operation.
A need exists, therefore, for lock detect circuits operating in combination with three state phase frequency detectors to provide near real time lock detect information at gigahertz operating speeds.